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US 2009/0257288 A1Published application
Apparatus and method for increasing data line noise tolerance
AssigneeMicron Technology, Inc.
InventorsFrankie F. Roohparvar, Chia-Shing Jason Yu, Jung-Sheng Hoei, Vishal Sarin
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Abstract
Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current source.
Claims21
A noise tolerance circuit for a memory, the noise tolerance circuit comprising:
- a first transistor having a drain/source coupled to a first node, a source/drain coupled to a bias current, and a gate coupleable to a reset signal;
- a second transistor having a drain/source coupled to the first node, a source/drain coupled to a reference voltage, and a gate coupled to a data line of the memory for pre-charging the data line with a threshold voltage.
A noise tolerance circuit for a memory having sense circuitry and a memory cell string, the noise tolerance circuit comprising:
- a first transistor and a second transistor gate coupleable to complementary inputs, the first transistor source to drain coupled between a bias voltage and a first node, and the second transistor source to drain coupled between a reference voltage and the first node;
- and
- a third transistor having a source/drain coupled to the first node, a drain/source coupled to a bias current, and a gate coupled to a data line of the memory.
A memory device comprising:
- an array of memory cells;
- control circuitry to read, write and erase the memory cells;
- and
- a noise tolerance circuit, comprising:
- a first transistor gate coupleable to a reset signal having a drain/source coupled to a first node and a source/drain coupled to a bias current;
- a second transistor having a drain/source coupled to the first node, a source/drain copuled to a reference voltage, and a gate coupled to a data line of the memory for pre-charging the data line with a threshold voltage.
3 more elements
A memory device comprising:
- an array of memory cells;
- control circuitry to read, write and erase the memory cells;
- and
- a noise tolerance circuit, comprising:
- a first transistor and a second transistor gate coupleable to complementary inputs, the first transistor source to drain coupled between a bias voltage and a first node, and the second transistor source to drain coupled between a reference voltage and the first node;
- and
- a third transistor having a source/drain coupled to the first node, a drain/source coupled to a bias current, and a gate coupled to a data line of the memory.
4 more elements
A processing system, comprising:
- a processor;
- and
- a memory coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising:
- an array of memory cells;
- control circuitry to read, write and erase the memory cells;
- and
- a noise tolerance circuit comprising:
- a first transistor and a second transistor gate coupleable to complementary inputs, the first transistor source to drain coupled between a bias voltage and a first node, and the second transistor source to drain coupled between a reference voltage and the first node;
- and
- a third transistor having a source/drain coupled to the first node, a drain/source coupled to a bias current, and a gate coupled to a data line of the memory.
7 more elements
A processing system, comprising:
- a processor;
- and
- a memory coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising:
- an array of memory cells;
- control circuitry to read, write and erase the memory cells;
- and
- a noise tolerance circuit comprising:
- a first transistor gate coupleable to a reset signal having a drain/source coupled to a first node and a source/drain coupled to a bias current;
- a second transistor having a drain/source coupled to the first node, a source/drain coupled to a reference voltage, and a gate coupled to a data line of the memory for pre-charging the data line with a threshold voltage.
6 more elements
A method of increasing noise tolerance in a memory, comprising:
- biasing a data line above a threshold voltage before sensing;
- and
- sensing with noise tolerance added into the data line by the biasing.
Dependencies are inferred from the claim text.