Memory and method of evaluating a memory state of a resistive memory cell

A memory device, comprising:

• a plurality of signal lines, wherein two directly adjacent signal lines each form a signal line pair;
• a plurality of resistive memory cells which are arranged at the signal lines and which are configured to be actively connected to respective signal lines;
• and
• a coupling device configured to alter an electric potential on a first signal line of a signal line pair, wherein a resistive memory cell is arranged at the first signal line, the altering of the electric potential being performed in the course of activating the resistive memory cell for actively connecting the resistive memory cell to the first signal line of the signal line pair in order to, starting from corresponding electric potentials on the signal lines of the signal line pair, generate a difference of potential between the signal lines.

A memory chip, comprising:

• a plurality of word lines;
• a plurality of bit lines, wherein two directly adjacent bit lines each form a bit line pair;
• a plurality of resistive memory cells which are arranged at cross points of word lines and bit lines and which are configured to be actively connected to respective bit lines by activating respective word lines, wherein resistive memory cells arranged at a word line are each arranged at one of the two bit lines of the bit line pairs;
• and
• a coupling device configured to capacitively alter an electric potential on a bit line of a bit line pair at which a resistive memory cell is arranged in the course of activating a word line associated with the resistive memory cell in order to, starting from corresponding electric potentials on the bit lines of the bit line pair, generate a difference of potential between the bit lines of the bit line pair.

A memory device, comprising:

• a plurality of signal lines, wherein two directly adjacent signal lines each form a signal line pair;
• a plurality of resistive memory cells which are arranged at the signal lines and configured to be actively connected to respective signal lines;
• and
• coupling means configured to capacitively alter an electric potential on a first signal line of a signal line pair, a resistive memory cell being arranged at the first signal line, in the course of activating the resistive memory cell for actively connecting the resistive memory cell to the first signal line of the signal line pair and, starting from essentially corresponding electric potentials on the signal lines of the signal line pair, for generating a difference of potential between the signal lines of the signal line pair.

A method of evaluating a memory state of a resistive memory cell, wherein the resistive memory cell is arranged at a first signal line of a signal line pair, comprising the steps of:

• activating the resistive memory cell for actively connecting the resistive memory cell to the first signal line;
• capacitively influencing the electric potential on the first signal line in order to, starting from essentially corresponding electric potentials on the first and second signal line, generate a difference of potential between the first and second signal line, wherein, after actively connecting the resistive memory cell to the first signal line, the capacitively influenced electric potential on the first signal line is changed based on the memory state of the resistive memory cell;
• and
• evaluating the memory state of the resistive memory cell by comparing the electric potentials on the first and second signal line.