Method and Apparatus for Computer Memory
AssigneeVNS Portfolio LLC
InventorCharles H. Moore
Life of this patent
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Abstract
A method and apparatus for forming computer memory 10 including RAM, ROM, Stacks and other registers. The memory array 10 includes a number of individual memory cells 40, 42, 44, 46 connected to each other by word lines 18, 20 and bit lines 30, 32. Memory cells 40, 42, 44, 46 word lines 18, 20 and bit lines 30, 32 are oriented in a manner to provide minimum line length and a substantialy square geometry. The method includes arranging the memory cells in an interleaved formation.
Claims18
A method for making computer memory comprised of memory cells on bit and word lines comprising the steps of, situating memory cells into lines;
- and interleveing memory cells.
A memory for a computer comprising:
- a plurality of interleaved memory cells;
- and a plurality of substantially straight bit lines connected to the memory cells for conveying information to and from the memory cells;
- and a plurality of substantially straight word lines connecting the memory cells for forming groups of memory cells.
An improved memory array for a computer having a plurality of memory cells and a plurality of bit lines and a plurality of word lines, the improvement comprising interweaving the memory cells to allow substantially straight bit lines and word lines.
Dependencies are inferred from the claim text.