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US 2009/0256254 A1Published application
Wafer level interconnection and method
AssigneeGeneral Electric Company
InventorsWilliam Edward Burdick, JR., Jeffrey Scott Erlbaum, Kaustubh Ravindra Nagarkar, Sandeep Shrikant Tonapi
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Abstract
A semiconductor assembly includes a semiconductor wafer including backside contact pads coupled to respective contact regions of different signal types and insulation separating the backside contact regions by signal type. The semiconductor assembly further includes metallization situated over at least a portion of the insulation and interconnecting the backside contact pads.
Claims22
A photovoltaic cell assembly comprising:
- (a) a photovoltaic (PV) cell including backside contact pads coupled to contact regions of different polarities and insulation separating the backside contact pads by polarity;
- and
- (b) metallization situated over at least a portion of the insulation and interconnecting the backside contact pads.
A semiconductor assembly comprising:
- a semiconductor wafer including contact pads on a common surface and coupled to respective contact regions of differing signal types and insulation separating the contact pads by signal type;
- and
- metallization situated over at least a portion of the insulation and interconnecting the contact pads.
A semiconductor assembly method comprising:
- providing a semiconductor wafer including contact pads on a common surface and coupled to respective contact regions of differing signal types;
- applying insulation at the wafer level to separate the contact pads by signal type;
- and
- applying metallization to interconnect the contact pads.
1 more element
Dependencies are inferred from the claim text.