Isolation Structure in Memory Device and Method for Fabricating the Isolation Structure

A method for fabricating an isolation structure in a memory device, the method comprising:

• forming a first trench in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate;
• forming a liner layer comprising a silicon nitride layer on the first and second trenches;
• forming a polysilazane spin on dielectric (SOD) layer on the liner layer to fill the first and second trenches;
• removing a portion of the SOD layer filling the second trench to expose the silicon nitride layer disposed on the second trench;
• oxidizing a portion of the exposed silicon nitride layer disposed on the second trench after removing the portion of the SOD layer, by using oxygen plasma and heat generated from the plasma;
• and
• forming a high density plasma (HDP) oxide layer to fill the second trench.

An isolation structure in a memory device, comprising:

• a semiconductor substrate comprising a first trench in a cell region and a second trench in a peripheral region, the first trench defining a first active region of the semiconductor substrate in which a channel of an n-channel metal oxide semiconductor (NMOS) transistor is to be formed, the second trench being wider than the first trench and defining a second active region of the semiconductor substrate in which a channel of a p-channel metal oxide semiconductor (PMOS) transistor is to be formed;
• a first liner layer disposed on the first trench and comprising a silicon nitride layer;
• a flowable dielectric layer disposed on the first liner layer to fill the first trench;
• a second liner layer disposed on the second trench and comprising an oxide layer;
• and
• a high density plasma (HDP) oxide layer disposed on the second liner layer to fill the second trench.