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US 2009/0256194 A1Published application
Semiconductor device with reduced resistance of bit lines and method for manufacturing the same
AssigneeHynix Semiconductor Inc.
InventorsKyung Do KIM, Seung Joo BAEK
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Abstract
A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the buried bit lines.
Claims25
A semiconductor device comprising:
- buried bit lines formed to be brought into contact with drain areas of vertical pillar transistors, the buried bit lines being arranged along a first direction in a silicon substrate, wherein the buried bit lines are formed of epi-silicon.
A semiconductor device comprising:
- a silicon substrate having a plurality of silicon pillars;
- gates formed to be buried in surfaces of lower portions of the silicon pillars;
- source areas formed in portions of the silicon pillars over the gates;
- drain areas formed in portions of the silicon substrate under the gates;
- buried bit lines formed of epi-silicon in the silicon substrate such that the buried bit lines are brought into contact with the drain areas of the vertical pillar transistors, the buried bit lines being arranged along a first direction among the vertical pillar transistors including the gates, the source areas, and the drain areas;
- a first insulation layer filled between the buried bit lines;
- word lines formed on the first insulation layer to connect the gates of the vertical pillar transistors, the word lines being arranged along a second direction perpendicular to the first direction;
- and
- a second insulation layer filled between the vertical pillar transistors including the word lines.
6 more elements
A method for manufacturing a semiconductor device, comprising the step of:
- forming buried bit lines by growing epi-silicon in a silicon substrate to be brought into contact with drain areas of vertical pillar transistors, the buried bit lines being arranged along a first direction.
A method for manufacturing a semiconductor device, comprising the steps of:
- etching a silicon substrate to form a plurality of silicon pillars;
- etching portions of the silicon substrate between the silicon pillars to define trenches extending along a first direction;
- growing epi-silicon in the trenches to form buried bit lines;
- isotropically etching surfaces of lower portions of the silicon pillars;
- forming gates buried in the lower portions of the silicon pillars which are isotropically etched;
- defining drain areas in portions of the silicon substrate under the gates;
- etching the buried bit lines such that the buried bit lines, which adjoin each other along a second direction perpendicular to the first direction, are separated from each other;
- filling a first insulation layer between and on the separated buried bit lines;
- forming word lines on the first insulation layer to connect the gates, the word lines being arranged along the second direction;
- filling a second insulation layer between the silicon pillars including the word lines;
- and
- defining source areas in portions of the silicon pillars over the gates such that vertical pillar transistors are constructed.
9 more elements
Dependencies are inferred from the claim text.