Method of Creating Alignment/Centering Guides for Small Diameter, High Density Through-Wafer Via Die Stacking

A method of manufacturing a semiconductor device, comprising:

• forming a plurality of alignment features in a wafer;
• dicing the wafer into a plurality of dies, such that each die comprises one or more of the plurality of alignment features;
• forming a plurality of through-wafer vias in a first die of the plurality of dies.

A die stack, comprising:

• a first die having a first plurality of alignment features and a plurality of through-wafer vias;
• and
• a second die having a second plurality of alignment features and a plurality of bond pads, wherein the second plurality of alignment features of the second die are configured to engage the first plurality of alignment features of the first die, such that the plurality of bond pads of the second die align with the plurality of through-wafer vias of the first die.

A system comprising:

• an electronic device comprising:
• a processor;
• one or more semiconductor devices, wherein the one more semiconductor devices comprises a die stack, wherein the die stack comprises a first die having a first plurality of alignment features and through-wafer vias.

A die stack, comprising:

• a first die having a first plurality of protrusions and a plurality of through-wafer vias;
• and
• a second die having a second plurality of protrusions, wherein the second plurality of protrusions are configured to engage the first plurality of protrusions.