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US 2009/0254784 A1Published application
Semiconductor memory device and system using semiconductor memory device
AssigneeNEC Electronics Corporation
InventorsMASATOSHI SONODA, YUUJIROU SHIMIZU, HIDEAKI ARIMA
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Abstract
A semiconductor memory device comprises a RAM (Random Access Memory), an ODT (On-Die Termination) circuits and a JTAG (Joint Test Action Group) circuit. The RAM is connected to a data input-output port. The ODT circuit is provided between the data input-output port and a termination port. The JTAG circuit controls the ODT circuit in response to an instruction such that the data input-output port and the termination port are electrically connected with each other.
Claims10
A semiconductor memory device comprising:
- a random access memory connected to a data input-output port;
- an on-die termination circuit provided between said data input-output port and a termination port;
- and
- a joint test action group circuit configured to control said on-die termination circuit in response to an instruction such that said data input-output port and said termination port are electrically connected with each other.
1 more element
A system comprising:
- a semiconductor memory device;
- and
- an instruction issuing unit configured to issue an instruction and output said instruction to said semiconductor memory device,
- wherein said semiconductor memory device comprises:
- a random access memory connected to a data input-output port;
- an on-die termination circuit provided between said data input-output port and a termination port;
- and
- a joint test action group circuit configured to control said on-die termination circuit in response to said instruction such that said data input-output port and said termination port are electrically connected with each other.
5 more elements
Dependencies are inferred from the claim text.