US 2009/0253235 A1Published application

Method of manufacturing semiconductor device with offset sidewall structure

AssigneeRenesas Technology Corp.

InventorsKazunobu Ota, Hirokazu Sayama, Hidekazu Oda

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Abstract

A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Claims1

Dependent claims

A method of manufacturing a semiconductor device comprising the steps of:

(a) preparing a semiconductor substrate having a major surface including a first NMOS region for forming a first NMOS transistor and a first PMOS region for forming a first PMOS transistor;
(b) forming a first gate insulating film in said first NMOS region and said first PMOS region and forming a first gate electrode and a second gate electrode on said first gate insulating film of said first NMOS region and said first PMOS region, respectively, and said first gate electrode and said second gate electrode each having side surfaces;
(c) after said step (b), forming an insulating film on said side surface of said first gate electrode and said side surfaces of said second gate electrode;
(d) after said step (c), implanting an N-type impurity into said first NMOS region;
(e) after said step (d), forming a silicon oxide film on said insulating film formed on said side surface of said second gate electrode;
(f) after said step (e), implanting P-type impurity into said first PMOS region.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/484,618Filed 15 Jun 2009
Priority: JP 2001-28891821 Sep 2001
Published: 8 Oct 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 64/516
Characterised by the insulating layers: the thicknesses being non-uniform
H10D 64/01302
Of electrodes having a conductor capacitively coupled to a semiconductor by an insulator: the insulator being formed after the semiconductor body,…
H10D 64/01332
The insulator being formed after the semiconductor body, the semiconductor being silicon: making the insulator
H10D 64/691
Characterised by the insulator, e.g. by the gate insulator: comprising metallic compounds, e.g. metal oxides or metal silicates

Family

Application10/212,252Continuation · filed 6 Aug 2002
Application11/743,021Continuation · filed 1 May 2007
Application12/484,618Continuation
US 2003/0059983 A1Published application
US 2007/0202634 A1Published application
US 7,220,637 B2Related patent
US 7,563,663 B2Related patent
US 7,998,802 B2Related patent
US 2009/0253235 A1This patent

From the US filing history. Foreign family members aren’t listed.

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