Semiconductor integrated circuit and layout method for the same

A layout method of a semiconductor integrated circuit, comprising:

• determining an interconnection layout of a semiconductor integrated circuit based on a netlist, a cell library and a connection rule;
• specifying a first interconnection layer, a second interconnection layer, a first via-contact and a second via-contact, wherein an interlayer insulating film is provided between said first interconnection layer and said second interconnection layer, and said first and second via-contacts are formed in said interlayer insulating film, and applied with a same voltage;
• checking whether or not a line between said first and second via-contacts extends along one of an X-axis and a Y-axis;
• checking a first interconnection pattern in said first interconnection layer of whether or not said first interconnection pattern is provided to connect said first and second via-contacts at their first ends, when the line extends along one of the X-axis and the Y-axis;
• checking whether or not said first interconnection pattern is a linear pattern;
• providing a redundant interconnection pattern to connect said first and second via-contacts at their second ends opposite to the first ends, when said first interconnection pattern is a linear pattern;
• and
• performing a design rule check on an interconnection layout with said redundant interconnection pattern added.

A computer-readable recording medium in which a computer-readable program code is stored to realize a layout method of a semiconductor integrated circuit, wherein said layout method comprises:

• determining an interconnection layout of a semiconductor integrated circuit based on a netlist, a cell library and a connection rule;
• specifying a first interconnection layer, a second interconnection layer, a first via-contact and a second via-contact, wherein an interlayer insulating film is provided between said first interconnection layer and said second interconnection layer, and said first and second via-contacts are formed in said interlayer insulating film, and applied with a same voltage;
• checking whether or not a line between said first and second via-contacts extends along one of an X-axis and a Y-axis;
• checking a first interconnection pattern in said first interconnection layer of whether or not said first interconnection pattern is provided to connect said first and second via-contacts at their first ends, when the line extends along one of the X-axis and the Y-axis;
• checking whether or not said first interconnection pattern is a linear pattern;
• providing a redundant interconnection pattern to connect said first and second via-contacts at their second ends opposite to the first ends, when said first interconnection pattern is a linear pattern;
• and
• performing g a design rule check on an interconnection layout with said redundant interconnection pattern added.