US 2009/0215278 A1Published application

Semiconductor device manufacturing method

AssigneeNEC Electronics Corporation

InventorTatsuya Suzuki

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Abstract

Prior to a step of providing a stress layer covering a first transistor, a second transistor and a gate structure, another silicon oxide film is formed over the second transistor to form a silicon oxide film with a predetermined thickness over the second transistor. By a step of removing the portion of the stress layer over the second transistor and the gate structure and leaving the portion of the stress layer over the first transistor, the silicon oxide film over the second transistor is prevented from becoming excessively thinner than the silicon oxide film over the first transistor. The source region and the drain region of the second transistor can be prevented from being shaved because of thinness of the silicon oxide film over the second transistor when removing silicon oxide films over the first transistor and second transistor.

Claims10

Dependent claims

A semiconductor device manufacturing method comprising:

forming a PMOS transistor and an NMOS transistor;
forming a silicon oxide film covering the PMOS transistor and the NMOS transistor;
providing, over the silicon oxide film, a stress layer covering the PMOS transistor and the NMOS transistor to apply a stress to one transistor of the PMOS transistor and the NMOS transistor;
removing a portion of the stress layer over the other transistor of the PMOS transistor and the NMOS transistor, and leaving a portion of the stress layer over the one transistor;
performing thermal treatment of the one transistor and the portion of the stress layer over the one transistor;
removing the portion of the stress layer over the one transistor;
forming another silicon oxide film over the other transistor to form a silicon oxide film with a predetermined thickness over the other transistor, the step of forming another silicon oxide film being performed prior to the step of providing the stress layer covering the PMOS transistor and the NMOS transistor,
or,
between the step of removing a portion of the stress layer over the other transistor and leaving a portion of the stress layer over the one transistor and the step of removing the portion of the stress layer over the one transistor;
and
removing a portion of the silicide oxide films over the PMOS transistor and the NMOS transistor.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/390,751Filed 23 Feb 2009
Priority: JP 2008-4270625 Feb 2008
Published: 27 Aug 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/792
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: comprising applied insulating layers, e.g. stress liners
H10D 84/0128
The components including insulated gates, e.g. IGFETs: manufacturing their channels
H10D 84/0133
Manufacturing their source or drain regions, e.g. silicided source or drain regions: manufacturing common source or drain regions between multiple…

Family

US 8,242,027 B2Related patent
US 2009/0215278 A1This patent

From the US filing history. Foreign family members aren’t listed.

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