Semiconductor device manufacturing method, semiconductor device manufacturing equipment, and computer readable medium

A semiconductor device manufacturing method comprising:

• forming a layer of first resist on a principal surface of each of a plurality of first substrates;
• exposing each of said plurality of first substrates to light in a predetermined pattern after said forming said layer of first resist;
• heating said plurality of first substrates separately by a plurality of heat treatment plates, after said exposing each of said plurality of first substrates;
• developing said each layer of first resist after said heating said plurality of first substrates;
• measuring resist pattern dimensions of said each layer of first resist after developing said each layer of first resist;
• performing a primary correction of a preset temperature for each of said plurality of heat treatment plates based on said measured resist pattern dimensions of said each layer of first resist;
• forming a layer of second resist having the same composition as that of said first resist on a principal surface of each of a plurality of second substrates;
• exposing each of said plurality of second substrates to light in the predetermined pattern after forming said layer of second resist;
• heating said plurality of second substrates separately by said plurality of heat treatment plates at said preset temperature corrected by said primary correction after said exposing each of said plurality of second substrates;
• developing said each layer of second resist after said heating said plurality of second substrates;
• etching each of said plurality of second substrates after said developing said each layer of second resist;
• measuring dimensions of an etched pattern that is formed on said principle surface of each of said plurality of second substrates after said etching each of said plurality of second substrates;
• and
• performing a secondary correction of the preset temperature for each of said plurality of heat treatment plates based on said measured dimensions of said etched pattern.

A semiconductor device manufacturing equipment comprising:

• a plurality of heat treatment plates for performing a post-exposure bake (PEB);
• a first storage section for storing a first relation, said first relation being an association relation between post-development resist pattern dimensions and a preset temperature during said PEB;
• a second storage section for storing a second relation, said second relation being an association relation between post-etching pattern dimensions and the preset temperature during said PEB;
• a primary correction section for obtaining post-development resist pattern dimension data for each of a plurality of first substrates processed separately by said plurality of heat treatment plates, and for primarily correcting the preset temperature for each of said plurality of heat treatment plates based on said first relation;
• and
• a secondary correction section for obtaining post-etching pattern dimension data for each of a plurality of second substrates processed separately by said plurality of heat treatment plates at the preset temperature corrected by said primary correction, and for secondarily correcting the preset temperature for each of said plurality of heat treatment plates based on said second relation.