Memory device and applications thereof
AssigneeThe Board of Trustees of the University of Illinois
InventorsJean-Pierre Leburton, Jeanlex Soares de Sousa, Gil De Aquino Farias, Valder Nogueira Freire
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Abstract
A system that incorporates teachings of the present disclosure may include, for example, a memory device having a memory cell to selectively store holes by photon and bias voltage induction as a representation of binary values. Additional embodiments are disclosed.
Claims27
A memory device, comprising:
- an n-type doped silicon substrate;
- a tunnel oxide layer formed on the n-type doped silicon substrate;
- a floating nanocrystal gate embedded in a control oxide layer and formed on the tunnel oxide layer;
- a drain region formed by implantation of a p-type dopant material in the n-type silicon substrate;
- a source region formed by implantation of a p-type dopant material in the n-type silicon substrate;
- a photon source coupled to the floating nanocrystal gate;
- and
- a control gate formed on the control oxide layer,
- wherein a first memory state is produced by:
- applying photons generated by the photon source to the floating nanocrystal gate to induce electron-hole pairs, and
- applying one or more bias voltages to at least one among the control gate, the drain region and the source region to induce a removal of electrons from the floating nanocrystal gate.
A memory device, comprising a memory cell to selectively store holes by photon and bias voltage induction as a representation of binary values.
A memory device, comprising an array of memory cells, each memory cell selectively stores holes by photon and bias voltage induction as a representation of binary values.
An apparatus, comprising:
- a memory array to selectively store holes by photon and bias voltage induction;
- and
- a computing device coupled to the memory array.
Dependencies are inferred from the claim text.