US 2009/0213637 A1 · Ferroelectric random access memory device

Abstract

An FRAM device can includes first ferroelectric capacitors, second ferroelectric capacitors, first plate lines and second plate lines. The first ferroelectric capacitors can be connected between word lines and bit lines. The second ferroelectric capacitors can be connected between the word lines and bit line bars. The first plate lines can be connected to upper electrodes of the first ferroelectric capacitors. The second plate lines can be connected to upper electrodes of the second ferroelectric capacitors. Thus, the first ferroelectric capacitors connected to the bit lines and the second ferroelectric capacitors connected to the bit line bars can be connected to the different plate lines, so that data can be output from any one of the bit line and the bit line bar. As a result, a layout of a core region can be simplified.

Claims15

Dependent claims

A ferroelectric random access memory (FRAM) device comprising:

first ferroelectric capacitors connected between word lines and bit lines;
second ferroelectric capacitors connected between the word lines and bit line bars;
first plate lines connected to upper electrodes of the first ferroelectric capacitors;
and
second plate lines connected to upper electrodes of the second ferroelectric capacitors.

2 more elements

A ferroelectric random access memory (FRAM) device comprising:

first active regions arranged in an odd row on a substrate at a first angle with respect to a first direction, each first active region having a shape defined by isolation regions adjacent the first active regions;
second active regions arranged in an even row on a substrate at the first angle with respect to the first direction, each second active region having a shape defined by isolation regions adjacent the second active regions;
word lines extending along the first direction on the first active regions and the second active regions, each of the word lines located on the first active regions and the second active regions;
bit lines crossing central portions of the first active regions along a second direction that is substantially perpendicular to the first direction;
bit line bars crossing central portions of the second active regions along the second direction;
first ferroelectric capacitors connected between the word lines and the bit lines;
second ferroelectric capacitors connected between the word lines and the bit line bars;
first plate lines connected to upper electrodes of the first ferroelectric capacitors and arranged between the word lines;
and
second plate lines connected to upper electrodes of the second ferroelectric capacitors and arranged between the word lines.

7 more elements

Dependencies are inferred from the claim text.

Ferroelectric random access memory device

Life of this patent

Ferroelectric random access memory device

Life of this patent

Abstract

Claims15