ESD protection for high-voltage-tolerance open-drain output pad
AssigneeElan Microelectronics Corporation
InventorsWu-Tsung Hsihe, Ming-Chun Chou, Ming-Dou Ker
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Abstract
A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.
Claims13
An ESD protection arrangement for a high-voltage I/O pad, comprising:
- a high-voltage NMOS transistor coupled between said high-voltage I/O pad and a low-voltage terminal, said high-voltage NMOS transistor having a parasitic component between a source and a drain thereof;
- and
- a trigger coupled to said high-voltage I/O pad and said parasitic component, to monitor the voltage on said high-voltage I/O pad in order to trigger said parasitic component when the voltage on said high-voltage I/O pad raises above a threshold value during an ESD event, so as to release an ESD current therethrough from said high-voltage I/O pad to said low-voltage terminal.
An ESD protection arrangement for a high-voltage I/O pad, comprising:
- a semiconductor structure formed on a substrate, including:
- a first region of a first conductive type;
- a second region of said first conductive type on said first region;
- and
- a third region of a second conductive type on said first region and coupled to a low-voltage terminal;
- a fourth region of said second conductive type on said first region and coupled to said high-voltage I/O pad;
- and
- a trigger coupled to said second region, to apply a voltage thereto;
- wherein said first, second, third and fourth regions constitute a parasitic BJT to be triggered when the voltage on said high-voltage I/O pad raises above a threshold value during an ESD event, so as to release an ESD current from said high-voltage I/O pad to said low-voltage terminal through said fourth, first and third regions.
Dependencies are inferred from the claim text.