Asymmetric Segmented Channel Transistors

A method of forming a semiconductor device, the semiconductor device comprising analog and digital devices, the method of forming the analog device sharing common processes with at least one digital device, the common processes comprising:

• depositing a gate dielectric layer over a semiconductor body;
• depositing a gate material layer over the gate dielectric;
• patterning the gate material layer to form a first gate and a first channel underneath the first gate, a second gate and a second channel underneath the second gate, wherein the first channel comprises a first length and width, and the second channel comprises a second length and width;
• implanting source/drain dopants and halo dopants to form a first transistor and a second transistor, wherein the first transistor comprises a first source, a first drain, the first source and drain being separated by a first channel, wherein the second transistor comprises a second source, a second drain, the second source and drain being separated by a second channel, wherein the first drain and the second source shared a common region, and wherein a threshold voltage of the first transistor is higher than a threshold voltage of the second transistor;
• and
• electrically coupling the first gate to the second gate.

A method of forming an integrated circuit, the integrated circuit manufactured in a CMOS flow and comprising analog and digital devices, the digital devices formed using the CMOS flow, wherein each step in the method of forming the analog devices shares a common process with at least one digital device in the CMOS flow, the steps comprising:

• depositing a first gate dielectric layer and a first gate dielectric layer over a semiconductor body;
• depositing a gate material layer over the first and second gate dielectric layer;
• patterning the gate material layer to form a first gate and a first channel underneath the first gate, a second gate and a second channel underneath the second gate, wherein the first channel comprises a first length and width, and the second channel comprises a second length and width;
• implanting source/drain dopants and halo dopants to form a first transistor and a second transistor, wherein the first transistor comprises a first source, a first drain, the first source and drain being separated by a first channel, wherein the second transistor comprises a second source, a second drain, the second source and drain being separated by a second channel, wherein the first drain and the second source shared a common region, and wherein a threshold voltage of the first transistor is higher than a threshold voltage of the second transistor;
• and
• electrically coupling the first gate to the second gate.

A method of designing an integrated circuit, the integrated circuit manufactured in a CMOS process common to the digital devices, the method comprising:

• identifying a target transistor with high analog gain in the integrated circuit;
• designing a first transistor comprising a first threshold voltage, a first gate length and a first width;
• designing a second transistor comprising a second threshold voltage, a second gate length and a second width;
• replacing the target transistor with the first transistor and the second transistor, wherein a drain of the first transistor and a source of the second transistor are electrically coupled, and wherein the gates of the first and second transistors are electrically coupled;
• calculating an output analog voltage gain of the combined first and second transistor;
• determining an error between the calculated output analog voltage gain and a target analog voltage gain;
• and
• redesigning the first threshold voltage and a second threshold voltage to lower the error below an acceptable level, wherein after the redesigning, the first threshold voltage is higher than the second threshold voltage.

A current mirror comprising:

• a first transistor having a first source region, a first drain region and a first gate region, the first source/drain region of the first transistor being coupled to the first gate region of the first transistor;
• a second transistor having a second source region, a second drain region and a second gate region, the second gate region of the second transistor being coupled to the first gate region of the first transistor;
• and
• a third transistor having a third source region, a third drain region and a third gate region, the third gate region of the third transistor being coupled to the first gate region of the first transistor and the third source region of the third transistor being coupled to the second drain region of the second transistor,
• wherein the first transistor and the third transistor each comprises an asymmetrical segmented transistor with high analog voltage gain, wherein the asymmetrical segmented transistor comprising floating source/drain region.