Method for forming a one-transistor memory cell and related structure

Abstract

According to one exemplary embodiment, a method for fabricating a one-transistor memory cell includes forming an opening by removing a portion of a gate stack of a silicon-on-insulator (SOI) device, where the SOI device is situated over a buried oxide layer. The method further includes forming a bottom gate of the one-transistor memory cell in a bulk substrate underlying the buried oxide layer. The method further includes forming a charge trapping region in the buried oxide layer. The charge trapping region is formed at an interface between a silicon layer underlying the gate stack and the buried oxide layer. The charge trapping region causes the one-transistor memory cell to have an increased sensing margin. The method further includes forming a top gate of the one-transistor memory cell in the opening. Also disclosed is an exemplary one-transistor memory cell fabricated utilizing the exemplary disclosed method.

Dependencies are inferred from the claim text.