Mirror bit memory device applying a gate voltage alternately to gate
AssigneeSpansion LLC
InventorFumiaki TOYAMA
Life of this patent
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Abstract
A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes: an ONO film including a charge storage layer on a semiconductor substrate; a plurality of bit lines each extending inside the semiconductor substrate; a plurality of interspaces each interposed between the adjacent bit lines; a plurality of gates each provided along the bit line on the ONO film above the interspaces; and a plurality of word lines electrically coupled with the corresponding gates formed on one of the interspaces, each extending to intersect with the bit lines. The two gates adjacent with each other in a width direction of the bit line are connected to different word lines.
Claims12
A semiconductor device comprising:
- a charge storage layer formed on a semiconductor substrate;
- a plurality of bit lines, each bit line of the plurality of bit lines extending inside the semiconductor substrate;
- a plurality of interspaces, each interspace of the plurality of interspaces being interposed between adjacent bit lines of the plurality of bit lines;
- a plurality of gates formed on the charge storage layer above the plurality of interspaces along a longitudinal direction of the plurality of bit lines;
- and
- a plurality of word lines electrically coupled with the plurality of gates formed on an interspace of the plurality of interspaces, each word line of the plurality of word lines extending to intersect with the plurality of bit lines,
- wherein, a first gate of the plurality of gates is adjacent to a second gate of the plurality of gates in a width direction of a bit line,
- and wherein the first gate is connected to a different word line than the second gate.
A method for manufacturing a semiconductor device, comprising:
- forming a charge storage layer on a semiconductor substrate;
- forming a plurality of bit lines to extend inside the semiconductor substrate;
- forming a plurality of gates on the charge storage layer above a plurality of interspaces, each gate of the plurality of gates interposed between the adjacent bit lines in the plurality of bit lines along a longitudinal direction of the plurality of bit lines;
- and
- forming a plurality of word lines electrically coupled with the plurality of gates on an interspace of the plurality of interspaces, each word line of the plurality of word lines extending to intersect with the plurality of bit lines such that adjacent gates of the plurality of gates are electrically coupled with different word lines in a width direction of the bit line.
Dependencies are inferred from the claim text.