System-on-chip with master/slave debug interface
AssigneeInfineon Technologies AG
InventorALBRECHT MAYER
Life of this patent
Estimating the term…
Abstract
A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface and a user interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system. The host system is connected to the at least one of the plurality of SOC ICs via the user interface.
Claims19
A System-on-Chip (SOC) integrated circuit (IC) debugging system comprising:
- a plurality of SOC ICs connected to a shared debug bus, at least one of the plurality of SOC ICs being a master SOC IC and comprising a master/slave debug interface and a user interface, wherein the master/slave debug interface is a bidirectional debug interface operable to send and receive debug data between the SOC ICs;
- and
- a host system connected directly or over several network or bus components to the at least one master SOC IC through the user interface.
A method of debugging a printed circuit board (PCB) through a user interface of a master system-on-chip (SOC) Integrated Circuit (IC), the PCB having at least one slave SOC IC connected to the master SOC via a debug bus, the method comprising:
- connecting a host system to the user interface of the master SOC IC;
- receiving debug data from the at least one slave SOC IC by the master SOC IC;
- temporarily storing the data by the master SOC IC;
- transferring the data from the master SOC IC to the host system through the user interface;
- and
- analyzing the transferred data at the host system.
Dependencies are inferred from the claim text.