US 2009/0155981 A1Published application

Method and apparatus for singulating integrated circuit chips

OwnerStephen P. Ayotte, Timothy S. Hayesinventors

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Abstract

A method of singulating integrated circuit chips. The method includes forming, from a bottom surface of a substrate, trenches part way through the substrate in the kerf regions surrounding integrated circuit regions previously formed in the substrate; placing a top surface of the substrate on a singulation fixture having compartments, the walls of the compartments fitting into the trenches in the substrate; and thinning the bottom surface of the substrate until the individual integrated circuit regions are singulated into individual integrated circuit chips.

Claims7

Dependent claims

A method comprising:

providing a substrate having an array of integrated circuit regions, each integrated circuit region of said array of integrated circuit regions separated by a first set of parallel kerf regions aligned in a first direction and a second set of parallel kerf regions aligned in a second direction, said substrate having a top surface and a bottom surface, said first and second directions perpendicular to each other and parallel to said top surface of said substrate, said first and second sets of parallel kerf regions intersecting to form a first grid pattern defining said array of integrated circuit regions;
forming a first set of parallel trenches in said first set of parallel kerf regions and forming a second set of parallel trenches in said second set of parallel kerf regions, said first and second sets of parallel trenches extending perpendicularly from said top surface of said substrate a first distance into said substrate, said first distance less than a second distance between said top and bottom surfaces of said substrate, said second distance measured perpendicularly from said top surface of said substrate;
providing a singulation fixture having an array of compartments, each integrated compartment of said array compartments separated by a first set of parallel walls aligned in a third direction and a second set of parallel walls aligned in a fourth direction, said singulation fixture having a top surface and a bottom surface, said third and fourth directions perpendicular to each other and parallel to said top surface of said singulation fixture, said first and second sets of parallel walls intersecting to form a second grid pattern defining said array of compartments, each compartment open at said top surface and closed at said bottom surface of said singulation fixture;
aligning and placing said substrate on said singulation fixture, said top surface of said substrate facing said top surface of said singulation fixture, said first and second sets of parallel trenches contacting top edges of said first and second set of parallel walls, each integrated circuit region of said set of integrated circuit regions aligned within corresponding and respective compartments of said singulation fixture;
and
thinning said substrate from said bottom surface of said substrate until individual integrated circuit regions of said substrate are singulated into individual integrated circuit chips, each integrated circuit chip contained in a respective compartment of said singulation fixture.

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Dependencies are inferred from the claim text.

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Abstract

A method comprising:

providing a substrate having an array of integrated circuit regions, each integrated circuit region of said array of integrated circuit regions separated by a first set of parallel kerf regions aligned in a first direction and a second set of parallel kerf regions aligned in a second direction, said substrate having a top surface and a bottom surface, said first and second directions perpendicular to each other and parallel to said top surface of said substrate, said first and second sets of parallel kerf regions intersecting to form a first grid pattern defining said array of integrated circuit regions;
forming a first set of parallel trenches in said first set of parallel kerf regions and forming a second set of parallel trenches in said second set of parallel kerf regions, said first and second sets of parallel trenches extending perpendicularly from said top surface of said substrate a first distance into said substrate, said first distance less than a second distance between said top and bottom surfaces of said substrate, said second distance measured perpendicularly from said top surface of said substrate;
providing a singulation fixture having an array of compartments, each integrated compartment of said array compartments separated by a first set of parallel walls aligned in a third direction and a second set of parallel walls aligned in a fourth direction, said singulation fixture having a top surface and a bottom surface, said third and fourth directions perpendicular to each other and parallel to said top surface of said singulation fixture, said first and second sets of parallel walls intersecting to form a second grid pattern defining said array of compartments, each compartment open at said top surface and closed at said bottom surface of said singulation fixture;
aligning and placing said substrate on said singulation fixture, said top surface of said substrate facing said top surface of said singulation fixture, said first and second sets of parallel trenches contacting top edges of said first and second set of parallel walls, each integrated circuit region of said set of integrated circuit regions aligned within corresponding and respective compartments of said singulation fixture;
and
thinning said substrate from said bottom surface of said substrate until individual integrated circuit regions of said substrate are singulated into individual integrated circuit chips, each integrated circuit chip contained in a respective compartment of said singulation fixture.

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