Dram with nanofin transistors

A method of forming a memory, comprising:

• forming a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions, wherein forming the nanofin transistor includes forming a crystalline nanofin structure with a cross-sectional thickness in a first direction less than a minimum feature length and a cross-sectional thickness in a second direction orthogonal to the first that corresponds to the minimum feature size, and wherein forming the nanofin transistor includes recrystallizing amorphous semiconductor into the crystalline nanofin structure on a crystalline substrate;
• connecting a data-bit line to the first source/drain region;
• connecting at least one word line to the surrounding gate of the nanofin transistor;
• and
• forming a stacked capacitor positioned above the nanofin structure and connected between the second source/drain region and a reference potential.

A method of forming a memory, comprising:

• forming a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions, wherein forming the nanofin transistor includes forming a crystalline silicon nanofin structure with a cross-sectional thickness in a first direction less than a minimum feature length and a cross-sectional thickness in a second direction orthogonal to the first that corresponds to the minimum feature size, and wherein forming the nanofin transistor includes etching a crystalline substrate to define a crystalline nanofin structure;
• connecting at least one word line to the surrounding gate of the nanofin transistor;
• and
• forming a stacked capacitor positioned above the nanofin structure and connected between the second source/drain region and a reference potential.