Failing address register and compare logic for multi-pass repair of memory arrays

An integrated circuit having a system for reallocating an address in a failing address register (FAR) when a corresponding redundant element fails, comprising:

• a set of FARs and an associated set of redundant elements, wherein each FAR maps to a corresponding redundant element;
• control logic for testing a set of elements and placing an address of each failing element into a FAR;
• control logic for testing each redundant element and marking a FAR as bad when a redundant element corresponding to the FAR fails;
• and
• control logic for readdressing the set of elements and placing an address of an element being readdressed into a new FAR when the address of the element being readdressed matches an address in a FAR that has been marked as bad.

An integrated circuit, comprising:

• a built in self test (BIST) system for testing elements and redundant elements during a BIST mode;
• a set of failing address registers (FARs) for storing addresses of failing elements discovered during BIST mode, wherein each FAR maps to a corresponding redundant element;
• an address bus;
• compare circuitry for comparing addresses placed on the address bus during a functional mode with addresses stored in the set of FARs;
• and
• control logic that utilizes the compare circuitry during BIST mode to compare an address on the address bus during a readdress phase with each FAR that has been marked as bad.