ALGORITHM FOR CHARGE LOSS REDUCTION AND Vt DISTRIBUTION IMPROVEMENT
AssigneeSpansion LLC
InventorsGwyn Robert Jones, Edward Franklin Runnion, Zhizheng Liu, Mark William Randolph
Life of this patent
Estimating the term…
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AssigneeSpansion LLC
InventorsGwyn Robert Jones, Edward Franklin Runnion, Zhizheng Liu, Mark William Randolph
Estimating the term…
Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states.
A method of programming or erasing one or more memory cells on a wordline of a memory array, the method comprising:
A method of programming or erasing one or more memory cells on a wordline of a memory array, the method comprising:
A memory device, comprising:
An electronic device, comprising:
Dependencies are inferred from the claim text.