Sensing and writing to magnetic random access memory (mram)

A magnetic memory write circuitry comprising:

• a magnetic memory element coupled to a bit line on one end;
• an access transistor coupled to an opposite end of the magnetic memory element and operative to select the magnetic memory element to be read or written thereto, the access transistor further coupled to a word line, the magnetic memory element being selected to be read from or written to when the bit line and word line are activated;
• a first inverter having an output coupled to the bit line and an input coupled to an input of the magnetic memory write circuit;
• a second inverter having an input coupled to the input of the magnetic memory write circuit and further having an output;
• and
• a third inverter having an input coupled to the output of the second inverter and an output coupled to the source of the access transistor and to virtual ground.

A method of formatting a reference magnetic memory element employed in reading a magnetic memory element of an array of magnetic memory comprising:

• setting the resistance of a first, second, third and fourth magnetic tunnel junction (MTJ) of a reference magnetic memory element to Rlow, said second MTJ coupled in parallel to the first MTJ and said fourth MTJ coupled in parallel to the first MTJ, said first and third MTJs coupled together in series and said second and fourth MTJs coupled together in series;
• pumping programming current through the first and second MTJs thereby changing their resistance values to Rhigh;
• and
• activating the formatting circuit causes programming of the first and second MTJs thereby increasing the resistance values of the first and second MTJs to Rhigh, the collective resistance value of the first and second MTJs being represented by the average of Rlow and Rhigh.

A method of sensing the state of a magnetic memory array comprising:

• generating current from a first current source;
• generating current from a second current source;
• receiving the first current source by a reference magnetic memory element;
• receiving the second current source by a magnetic memory element to be read;
• enabling a criss-cross latch that senses the voltage of a reference magnetic memory element and the voltage of a magnetic memory element to be read;
• waiting a first predetermined period of time to initiate placing the criss-cross latch in a particular direction;
• enabling initiation of placing the criss-cross latch in a particular direction;
• waiting a second predetermined period of time;
• deactivating the initiation;
• and
• amplifying and latching the state of the magnetic memory array.