US 2009/0152626 A1 · Super Halo Formation Using a Reverse Flow for Halo Implants

Abstract

Shrinking dimensions of MOS transistors in integrated circuits requires tighter distributions of dopants in pocket regions from halo ion implant processes. In conventional fabrication process sequences, halo dopant distributions spread during source/drain anneals. The instant invention is a method of fabricating MOS transistors in an integrated circuit in which halo ion are performed after source/drain anneals. In the inventive method, source/drain spacers on MOS gate sidewalls are removed prior to halo ion implant processes. Spacers to offset metal silicide are formed after halo implants and may be of low-k dielectric material to reduce gate to drain capacitance. A compressive stress layer may be deposited on MOS gates after source/drain spacers are removed for greater stress transfer efficiency to the MOS gates. An integrated circuit embodying the inventive method is also disclosed.

A method of forming an integrated circuit, comprising the steps of:

providing a semiconductor substrate;
forming a p-type well in said semiconductor substrate at a top surface of said semiconductor substrate;
forming an n-type well in said semiconductor substrate at said top surface of said semiconductor substrate;
forming a gate dielectric layer on a top surface of said n-type well and a top surface of said p-type well;
forming an n-channel MOS transistor gate on a top surface of said gate dielectric layer over said p-type well;
forming an p-channel MOS transistor gate on a top surface of said gate dielectric layer over said n-type well;
forming NMDD spacers less than 20 nm thick on lateral surfaces of said n-channel MOS transistor gate;
ion implanting a first set of n-type dopant atoms into said p-type well adjacent to said n-channel MOS transistor gate;
forming PMDD spacers less than 20 nm thick on lateral surfaces of said p-channel MOS transistor gate;
ion implanting a first set of p-type dopant atoms into said n-type well adjacent to said p-channel MOS transistor gate;
annealing said semiconductor substrate so that any damage to said semiconductor substrate from said step of ion implanting said first set of n-type dopant atoms and said step of ion implanting said first set of p-type dopant atoms is substantially repaired;
forming NSD spacers more than 30 nm thick on lateral surfaces of said n-channel MOS transistor gate;
ion implanting a second set of n-type dopants into said p-type well adjacent to said NSD spacers;
forming PSD spacers more than 30 nm thick on lateral surfaces of said p-channel MOS transistor gate;
ion implanting a second set of p-type dopants into said n-type well adjacent to said PSD spacers;
annealing said semiconductor substrate so that any damage to said semiconductor substrate from said step of ion implanting said second set of n-type dopant atoms and said step of ion implanting said second set of p-type dopant atoms is substantially repaired;
removing material from said NSD spacers by an etching process;
ion implanting a third set of p-type dopants into said p-type well adjacent to said n-channel MOS transistor gate after said step of removing material from said NSD spacers;
removing material from said PSD spacers by an etching process;
ion implanting a third set of n-type dopants into said n-type well adjacent to said p-channel MOS transistor gate after said step of removing material from said PSD spacers;
annealing said semiconductor substrate so that any damage to said semiconductor substrate from said step of ion implanting said third set of p-type dopant atoms and said step of ion implanting said third set of n-type dopant atoms is substantially repaired;
forming a first set of silicide spacers on lateral surfaces of said n-channel MOS transistor gate;
forming a second set of silicide spacers on lateral surfaces of said p-channel MOS transistor gate;
and
forming a metal silicide layer on said top surface of said p-type well adjacent to said first set of silicide spacers and on said top surface of said n-type well adjacent to said second set of silicide spacers

22 more elements

Super Halo Formation Using a Reverse Flow for Halo Implants

Life of this patent

Super Halo Formation Using a Reverse Flow for Halo Implants

Life of this patent

Abstract

Claims19