DRAM Cell Transistor Device and Method

A semiconductor integrated circuit apparatus, comprising:

• a substrate comprising a surface region;
• a well structure within the substrate;
• a first region within the well structure, the first region being characterized by impurities for threshold voltage adjustment;
• a second region within the well structure, the second region being substantially free of impurities for threshold voltage adjustment;
• isolation regions within the well structure;
• a channel region within the first region;
• a gate dielectric layer overlying the channel region;
• a gate stack overlying the gate dielectric layer, the gate stack comprising a silicide layer overlying a polysilicon layer;
• LDD structures on sides of the channel region;
• spacers on sides of each of the gate stacks;
• a source region and a drain region;
• and
• a contact structure over the source region, a junction between the contact structure and the source region being substantially within the second region.

A DRAM memory cell device, comprising:

• a substrate;
• a plurality of isolation regions formed in the substrate;
• a P-well region formed in the substrate, the P-well region being characterized by p-type dopants of a first concentration;
• a channel region within the P-well region, the channel region being characterized by p-type dopants of a second concentration, the second concentration being higher than the first concentration;
• an N-type drain region formed in the P-well region and adjacent to the channel region;
• an N-type source region formed in the P-well region and adjacent to the channel region;
• a conductive structure forming a contact with the source region, the source region being characterized by p-type dopants of the first concentration;
• and
• a charge storage capacitor electrically coupled to the conductive structure.