Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors

A method comprising:

• providing an array of discrete semiconductor bodies on a substrate, wherein each semiconductor body includes a first end and a second end;
• growing a first set of silicon germanium layers on the first ends of the semiconductor bodies of the array until the silicon germanium layers of the first set contact one another along interfacial boundaries;
• and
• growing a second set of silicon germanium layers on the second ends of the semiconductor bodies of the array until the silicon germanium layers of the second set contact one another along interfacial boundaries.

A method comprising:

• forming an array of semiconductor bodies on a substrate, each semiconductor body having a top surface, a pair of laterally opposite sidewalls, a first end, and a second end;
• forming a gate electrode across the array of semiconductor bodies, the gate electrode having a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies;
• etching away portions of the semiconductor bodies not covered by the gate electrode;
• epitaxially depositing silicon germanium on the etched portions of the semiconductor bodies, wherein the deposition continues until the silicon germanium on each semiconductor body comes into contact with silicon germanium on at least one adjacent semiconductor body along an interfacial boundary.

A method comprising:

• forming an array of semiconductor bodies on a substrate, each semiconductor body having a top surface and a pair of laterally opposite sidewalls;
• forming a gate electrode across the array of semiconductor bodies, the gate electrode having a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies;
• etching a pair of recesses in each semiconductor body on opposite sides of the gate electrode;
• epitaxially depositing silicon germanium within the pair of recesses of each semiconductor body to form source and drain regions;
• and
• continuing to epitaxially deposit the silicon germanium until the silicon germanium on each semiconductor body comes into contact with the silicon germanium on at least one adjacent semiconductor body along an interfacial boundary.

A method comprising:

• depositing a layer of silicon germanium on a substrate;
• patterning the silicon germanium layer using a photolithography process to form a common source region and a common drain region connected by an array of semiconductor bodies;
• forming a gate dielectric layer on each semiconductor body of the array;
• and
• forming a gate electrode across the array of semiconductor bodies atop the gate dielectric layers.