Feature Dimension Measurement

A semiconductor device comprising:

• a substrate;
• a device area comprising:
• a gate layer formed over the substrate and including at least one gate;
• an interlayer dielectric layer formed over the gate layer;
• and
• a damascene layer formed over the interlayer dielectric layer and including at least one interconnection;
• a test area comprising:
• a reflective layer formed over the substrate;
• a transparent layer formed over the reflective layer and having a thickness substantially equal to the thickness of the interlayer dielectric layer;
• and
• a grating pattern layer formed over the transparent layer, having a thickness substantially equal to the thickness of the damascene layer, and comprising a grating pattern comprising a plurality of dielectric regions, a plurality of grating lines and a resistivity test line.

A semiconductor device comprising:

• a substrate comprising a plurality of semiconductor dies separated by cut lines;
• a device region comprising:
• a gate layer formed over the substrate and including a plurality of gates;
• an interlayer dielectric layer formed over the gate layer and comprising a plurality of vias;
• and
• a damascene layer formed over the interlayer dielectric layer and comprising a plurality of copper lines coupled to the plurality of vias in the interlayer dielectric layer;
• a test region formed at a cut-line of the substrate comprising:
• a reflective layer formed over the substrate;
• a transparent layer formed over the reflective layer and having a thickness substantially equal to the thickness of the interlayer dielectric layer;
• and
• a grating pattern layer formed over the transparent layer, having a thickness substantially equal to the thickness of the damascene layer, and comprising a grating pattern comprising a plurality of dielectric regions, a plurality of grating lines and a resistivity test line.