Thick metal interconnect with metal pad caps at selective sites and process for making the same

A process for providing a power metal interconnection (115) with a metal cap (125/127) on a substrate (100) having at least one exposed interconnect metal feature (107), said process comprising the steps of:

• (a) depositing at least one dielectric layer (112) over at least one interconnect metal feature (107) on said substrate (100);
• (b) photolithographically defining a pattern for a power metal interconnect (115) and etching said dielectric layer (112) to expose a portion of said interconnect metal feature (107);
• (c) sputter depositing a seed layer (114/113), wherein said seed layer (114/113) comprises a first barrier layer (114) and a copper power metal layer (113);
• (d) defining a negative photoresist pattern for said power metal interconnect (115) over said substrate (100);
• (e) electroplating a copper power metal layer (115) using said seed layer (114/113) as an electrode;
• (f) removing said photoresist and wet etching said seed layer (114/113) using said electroplated copper (115) as mask, and forming a copper power metal interconnect (115);
• (g) depositing at least one layer of a flowable dielectric (116) over said substrate (100);
• (h) photolithographically defining a pattern for a pad-via layout (135) in said flowable dielectric layer (116);
• (i) opening a pad-via (135) to expose at least a portion of said copper power metal interconnect (115);
• (j) electroless Nickel-Phosphorus plating (125) said exposed copper surface (115) and forming a Nickel-Phosphorus wire bond pad (125) on top of said copper power metal interconnect (115);
• and
• (k) plating said Nickel-Phosphorus wire bond pad (125) with a layer of gold (127).

A process for providing a power metal interconnection (115) with protective surface coating (120/121) on a substrate (100) having at least one exposed interconnect metal feature (107), said process comprising the steps of:

• (a) depositing a dielectric layer (112) over said interconnect metal feature (107) and said substrate (100);
• (b) defining a pattern for a power metal interconnect (115) and etching said dielectric layer (112) to expose said interconnect metal feature (107);
• (c) sputter depositing a seed layer (114/113) comprising of a first barrier metal layer (114) and a first copper power metal layer (113);
• (d) defining a negative photoresist pattern for said power metal interconnect (115) over said substrate (100);
• (e) electroplating a second copper power metal layer (115) using said seed layer (114/113) as an electrode;
• (f) removing said photoresist and wet etching said seed layer (114/113) using said electroplated copper layer (115) as mask, and forming a copper power metal interconnect (115);
• (g) electroless Nickel-Phosphorus plating (120) said copper power metal interconnect (115) and encasing at least a portion of said copper power metal interconnect (115) with a coating of a Nickel-Phosphorus layer (120), and
• (h) plating said coating of said Nickel-Phosphorus layer (120) with a layer of gold (121).

A process of providing power metal interconnections (115) on a substrate (100) having at least one exposed interconnect metal feature (107), said process comprising the steps of:

• (a) depositing a dielectric layer (112) over said interconnect metal feature (107) and said substrate (100);
• (b) photolithographically defining a pattern for a power metal interconnect (115) and etching said dielectric layer (112) to expose said interconnect metal feature (107);
• (c) sputter depositing a seed layer (114/113), wherein said seed layer (114/113) comprises of a barrier layer (114) and a gold layer (113);
• (d) defining a negative photoresist pattern for said power metal interconnect (115);
• (e) electroplating a gold power metal (115) using said seed layer (114/113) as an electrode;
• and
• (f) removing said photoresist and wet etching said seed layer (114/113) using said electroplated gold (115) as mask forming a gold power metal interconnect (115), and wherein said gold power metal interconnect (115) comprises said sputter deposited gold layer (113) and said electroplated gold power metal layer (115).