Semiconductor device

A semiconductor device comprising a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from said logic circuits, wherein

• each of said judging circuit comprises:
• a first clock control unit for controlling a transmission of a clock signal based on an enable signal;
• a first register for capturing the data from said logic circuits in a predetermined timing of said clock signal controlled by said first clock control unit;
• a delay unit for delaying said clock signal;
• a second clock control unit for controlling a transmission of said clock signal, which has passed through said delay unit, based on said enable signal;
• a second register logically equivalent to said first register for capturing the data from said logic circuit in a predetermined timing of said clock signal controlled by said second clock control unit;
• a comparator for comparing an output of said first register and an output of said second register to output an error signal;
• a fail safe circuit inserted into a line of said enable signal to be input to said second clock control unit, for avoiding a glitch from being superimposed on said clock signal, which has passed through said delay unit;
• and
• a third register inserted into a previous stage of said second clock control unit for judging contents of a event of said enable signal.

A semiconductor device comprising a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from said logic circuits, wherein

• each of said judging circuits comprises:
• a first clock control unit for controlling a transmission of a clock signal based on an enable signal;
• a first register for capturing the data from said logic circuits in a predetermined timing of said clock signal controlled by said first clock control unit;
• a first delay unit for delaying said clock signal;
• a second clock control unit for controlling a transmission of said clock signal, which has passed through said first delay unit, based on said enable signal;
• a second register logically equivalent to said first register for capturing the data from said logic circuits in a predetermined timing of said clock signal controlled by said second clock control unit;
• and
• a comparator for comparing an output from said first register and an output from said second register to output an error signal, and wherein said semiconductor device further comprises a detection circuit for detecting a setup violation of said enable signal, with respect to a plurality of said judging circuits for controlling said clock signal by said same enable signal.

A semiconductor device comprising a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from said logic circuits, wherein

• each of said judging circuits comprises:
• a first register for capturing the data from said logic circuits in a predetermined timing of a clock signal;
• a delay unit for delaying said clock signal;
• a second register logically equivalent to said first register for capturing the data from said logic circuits in a predetermined timing of said clock signal, which has passed through said logic unit;
• a comparator for comparing an output from said first register and an output from said second register to output an error signal;
• a selection circuit for selecting any of the output from said first register and the output of said second register based on said error signal to transmit to said logic circuit of a subsequent stage;
• and
• a differentiation circuit for filtering a glitch of said error signal and detecting a rising edge of said error signal, thereby controlling to stop said clock signal for a predetermined period.

A semiconductor device comprising a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from said logic circuits, wherein

• each of said judging circuits comprises:
• a first register for capturing the data from said logic circuits in a predetermined timing of a clock signal;
• a delay unit for delaying said clock signal;
• a second register logically equivalent to said first register for capturing the data from said logic circuits in a predetermined timing of said clock signal, which has passed through said logic unit;
• a comparator for comparing an output from said first register and an output from said second register to output an error signal;
• and
• a metastability detection circuit for detecting metastable in a subsequent stage of said first register, wherein
• said semiconductor device allows said judging circuit to always judge as malfunction at the time of detection of said metastable, based on an output of said metastability detection circuit.

A semiconductor device comprising a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from said logic circuit, wherein

• said judging circuit comprises:
• a first register for capturing the data from said logic circuits in a predetermined timing of a clock signal;
• a delay unit for delaying said clock signal;
• a second register logically equivalent to said first register for capturing the data from said logic circuits in a predetermined timing of said clock signal, which has passed through said delay unit;
• and
• a comparator for comparing an output from said first register and an output from said second register to output an error signal, and wherein
• a plurality of said judging circuits are grouped in unit capable of controlling a delay amount of said delay unit, and said delay unit of the delay amount corresponding to said judging circuit belonging to each group is provided.

A semiconductor device comprising a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from said logic circuits, wherein

• each of said judging circuits comprises:
• a first register for capturing the data from said logic circuits in a predetermined timing of a clock signal;
• a delay unit for delaying said clock signal;
• a second register logically equivalent to said first register for capturing the data from said logic circuits in a predetermined timing of said clock signal, which has passed through said delay unit;
• and
• a comparator for comparing an output from said first register and an output from said second register to output an error signal, and wherein
• any of a lock-up latch and an inverted flip-flop circuit is inserted on a path on which a hold violation occurs in a previous stage of said judging circuit.