Wiring structure in semiconductor device and method of fabricating wiring structure in semiconductor device

A method of fabricating a wiring structure in a semiconductor device, comprising:

• forming a first insulation layer on a substrate having a first contact region and a second contact region;
• forming a first pad and a second pad on the first contact region and the second contact region, respectively, the first and the second pads being higher than the first insulation layer;
• forming a blocking layer pattern on the first insulation layer between the first pad and the second pad, the blocking layer pattern being higher than the first and the second pads;
• forming a second insulation layer on the blocking layer pattern, the first pad and the second pad;
• forming an opening by partially etching the second insulation layer to expose the first pad and the blocking layer pattern;
• forming a spacer on a sidewall of the opening;
• and
• forming a plug on the first pad to fill the opening.

A method of manufacturing a semiconductor device, comprising:

• forming a conductive structure on a substrate, the conductive structure including a first contact region and a second contact region formed on the substrate;
• forming a first insulation layer on the substrate to cover the conductive structure;
• forming a blocking layer pattern on the first insulation layer;
• forming a first contact hole and a second contact hole through the first insulation layer using the blocking layer pattern to expose the first contact region and the second contact region, respectively;
• forming a first pad and a second pad in the first contact hole and the second contact hole, respectively, the first and the second pads being higher than the first insulation layer, and lower than the blocking layer pattern;
• forming a second insulation layer on the blocking layer pattern, the first pad and the second pad;
• forming a third contact hole by partially etching the second insulation layer to expose the second pad;
• forming a bit line structure on the second insulation layer to fill the third contact hole;
• forming a third insulation layer on the second insulation layer to cover the bit line structure;
• forming an opening by partially etching the third insulation layer and the second insulation layer to expose the first pad and the blocking layer pattern;
• forming a spacer on a sidewall of the opening;
• and
• forming a plug on the first pad to fill the opening.