Semiconductor device having trench isolation region and methods of fabricating the same

Abstract

A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively.

Dependencies are inferred from the claim text.