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US 2009/0020810 A1Published application
Method of Forming Power Device Utilizing Chemical Mechanical Planarization
AssigneeFairchild Semiconductor Corporation
InventorBruce Douglas Marchant
Life of this patent
Estimating the term…
Abstract
A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.
Claims8
1-51. (canceled)
A field effect transistor comprising:
- a plurality of active gate trenches in a silicon region, each active gate trench including a recessed gate electrode;
- a gate runner trench in the silicon region, the gate runner trench being contiguous with the plurality of active gate trenches, the gate runner trench including a recessed gate runner, the recessed gate runner being contiguous with and thus in electrical contact with the recessed gate electrodes, wherein the gate runner trench has a width greater than a width of each of the plurality of active gate trenches.
58-106. (canceled)
Dependencies are inferred from the claim text.