Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices

A non-volatile memory device, comprising:

• a source region and a drain region disposed on a substrate;
• a floating gate polysilicon layer disposed over the source and drain regions;
• a first silicon oxynitride layer disposed over the floating gate;
• a high-k dielectric layer disposed over the first silicon oxynitride layer;
• and
• a second silicon oxynitride layer disposed over the high-k dielectric layer;
• a control gate polysilicon layer disposed over the high-k dielectric layer.

A method of fabricating a non-volatile memory device, comprising:

• depositing a floating gate polysilicon layer on a substrate;
• depositing a silicon oxide layer over the substrate;
• exposing the silicon oxide layer to a nitridation process to form a silicon oxynitride layer;
• exposing the substrate to a thermal annealing process;
• depositing a high-K dielectric material over the silicon oxynitride layer;
• exposing the substrate to a post deposition annealing process;
• exposing the high-K material to a nitridation process to form a nitrided high-k material;
• exposing the nitrided high-k material to a post nitridation annealing process;
• depositing a second silicon oxide layer over the nitrided high-k material;
• exposing the substrate to a nitridation process to form a second silicon oxynitride layer;
• and
• exposing the substrate to a post nitridation annealing process.