Test structures of a semiconductor device and methods of forming the same
AssigneeSamsung Electronics Co., Ltd.
InventorJae-Pil Lee
Life of this patent
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Abstract
A test structure including a transistor, a conductive pattern and a pad unit is provided. The transistor may be formed on a substrate having circuit patterns. The conductive pattern is electrically connected to the transistor. The conductive pattern may be used in aligning the circuit patterns and/or sensing plasma damage to the semiconductor device. The conductive pattern may be used in reducing etching damage to the circuit patterns and sensing plasma damage to the semiconductor device. The pad unit is electrically connected to the transistor, and provides electrical signals to the transistor. The conductive pattern may serve as an antenna pattern and/or an align/overlay pattern or a dummy pattern.
Claims24
A test structure of a semiconductor device, comprising:
- a transistor on a substrate having circuit patterns;
- a conductive pattern electrically connected to the transistor, the conductive pattern being used in aligning the circuit patterns and sensing plasma damage to the semiconductor device;
- and
- a pad unit electrically connected to the transistor, the pad unit providing electrical signals to the transistor.
A test structure of a semiconductor device, comprising:
- a transistor on a substrate having circuit patterns;
- a conductive pattern electrically connected to the transistor, the conductive pattern being used in reducing etching damage to the circuit patterns and sensing plasma damage to the semiconductor device;
- and
- a pad unit electrically connected to the transistor, the pad unit providing electrical signals to the transistor.
A method of forming a test structure of a semiconductor device, comprising:
- forming a transistor on a substrate having circuit patterns;
- forming a conductive pattern electrically connected to the transistor, the conductive pattern being used in aligning the circuit patterns and sensing plasma damage to the semiconductor device;
- and
- forming a pad unit electrically connected to the transistor, the pad unit providing electrical signals to the transistor.
A method of forming a test structure of a semiconductor device, comprising:
- forming a transistor on a substrate having circuit patterns;
- forming a conductive pattern electrically connected to the transistor, the conductive pattern being used in reducing etching damage to the circuit patterns and sensing plasma damage to the semiconductor device;
- and
- forming a pad unit electrically connected to the transistor, the pad unit providing electrical signals to the transistor.
Dependencies are inferred from the claim text.