Output buffer circuit

An output buffer circuit comprising:

• an input terminal receiving an input signal;
• a delay circuit coupled from said input terminal, said delay circuit having a plurality of delay elements to delay said input signal, said plurality of delay elements comprising:
• a first delay path coupled to a first node, said first delay path performing time shifting transmission for said input signal, thereby extracting a first signal from said first node;
• a second delay path coupled to a second node, said second delay path performing time shifting transmission longer than a delay time of said first delay path for said input signal, thereby extracting a second signal from said second node;
• and
• a third delay path coupled to a third node, said third delay path performing time shifting transmission longer than a delay time of said second delay path for said input signal, thereby extracting a third signal from said third node;
• an output terminal;
• a select terminal receiving a select signal;
• a first multiplexing driver selectively coupled from one of said input terminal and said first node in response to said select signal to drive said output terminal in response to one of said input signal and said first signal, respectively,
• wherein a path of said first delay path and said first multiplexing driver is arranged and configured to perform a logically NON reversible function in one pass through said first delay path and said first multiplexing driver via said first node, and a path of said input terminal and said first multiplexing driver is arranged and configured to perform a logically NON reversible function in one pass through said input terminal and said first multiplexing driver;
• a second multiplexing driver selectively coupled from one of said input terminal and said second node in response to said select signal to drive said output terminal in response to one of said input signal and said second signal, respectively;
• and
• a third multiplexing driver selectively coupled from one of said input terminal and said third node in response to said select signal to drive said output terminal in response to said one of input signal and said third signal, respectively,
• wherein a path of said third delay path and said third multiplexing driver is arranged and configured to perform a logically reversible function in one pass through said third delay path and said third multiplexing driver via said third node, and a path of said input terminal and said third multiplexing driver is arranged and configured to perform a logically reversible function in one pass through said input terminal and said third multiplexing driver.