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US 2009/0015275 A1Published application
Ultra-Fine Area Array Pitch Probe Card
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHsu Ming Cheng
Life of this patent
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Abstract
A system and a method of testing a semiconductor die is provided. An embodiment comprises a printed circuit board connected to a space transformation layer, which is connected to a substrate. The substrate uses through silicon vias and a redistribution layer to reduce the pitch of the connections beyond the historical limitations. A probe head using Cobra-style probe pins is connected to the redistribution layer through C4 bumps.
Claims20
A semiconductor device test structure comprising:
- a printed circuit board;
- a space transformation layer comprising conductive lines, the conductive lines electrically connected to the printed circuit board by first connectors with a first pitch;
- a substrate having vias formed therein, the vias electrically connected to the conductive lines through second connectors, the second connectors having a second pitch smaller than the first pitch, the substrate located opposite the printed circuit board;
- redistribution lines connected to respective ones of the vias, the redistribution lines located on the substrate opposite the space transformation layer;
- and
- third connectors electrically connected to respective ones of the redistribution lines, the third connectors having a third pitch that is smaller than the second pitch.
3 more elements
A semiconductor device test structure comprising:
- an array of probe pins having a first pitch;
- a substrate with first connectors formed thereon, the first connectors in electrical contact with respective ones of the probe pins;
- redistribution lines located on the substrate facing the probe pins, the redistribution lines in electrical connection with the first connectors;
- vias located through the substrate, the vias in electrical connection with respective ones of the redistribution lines and having a second pitch that is larger than the first pitch;
- a space transformation layer located on the opposite side of the substrate from the probe pins, the spacer transformation layer comprising conductive material electrically connected to the vias through second connectors;
- and
- a printed circuit board located on the opposite side of the space transformation layer than the substrate, the printed circuit board being electrically connected to the conductive material through third connectors, the third connectors having a third pitch larger than the second pitch.
4 more elements
A semiconductor device test structure comprising:
- a substrate with vias located therein, the substrate having a first side and a second side opposite the first side, the vias having a first pitch;
- redistribution lines located on the first side of the substrate and in electrical connection with respective ones of the vias;
- and
- probe pin connectors located on the first side of the substrate, the probe pin connectors having a second pitch that is smaller than the first pitch.
1 more element
Dependencies are inferred from the claim text.