Semiconductor chip, method of fabricating the same and stack package having the same

A semiconductor chip stack package comprising:

• a first semiconductor chip including a semiconductor device formed on a wafer, a via formed in the via hole and a metal interconnection electrically connected to the semiconductor device, the metal interconnection including a pad region;
• a conductive member having a first surface contacting the pad region and an exposed second surface;
• and
• a second semiconductor chip stacked on the first semiconductor chip using the exposed second surface of the conductive member,
• wherein the conductive member electrically connects the first semiconductor chip to the second semiconductor chip.

A method of fabricating a semiconductor chip comprising:

• forming a semiconductor device formed on the wafer;
• and then
• forming a first dielectric layer on the semiconductor device;
• and then
• forming a first metal interconnection on the first dielectric layer;
• and then
• sequentially forming a second dielectric layer on the first dielectric layer and the first metal interconnection and a third dielectric layer on the second dielectric layer;
• and then
• forming a second metal interconnection in the third dielectric layer;
• and then
• forming a first nitride layer on the third dielectric layer and the second metal interconnection, the first protective layer having a first hole exposing a portion of the second metal interconnection;
• and then
• forming a via extending through the wafer, the dielectric layers and the first nitride layer, the via having an exposed lower end and an exposed upper end;
• and then
• forming a third metal interconnection on the exposed upper end of the via and the second metal interconnection exposed by the first hole and the second hole.