Wafer level stacked package having via contact in encapsulation portion and manufacturing method thereof

A wafer level stacked package with a via contact in an encapsulation portion, the wafer level stacked package comprising:

• a first semiconductor chip with an active region facing upward;
• a first encapsulation portion formed along an edge of the first semiconductor chip;
• a first wiring pattern connected to bond pads of the first semiconductor chip, the first wiring pattern formed above the first semiconductor chip and extending above the first encapsulation portion;
• a second semiconductor chip electrically connected to the first semiconductor chip via a bump, the second semiconductor chip having a size smaller than the first semiconductor chip;
• a second encapsulation portion formed along an edge of the second semiconductor chip;
• a third semiconductor chip mounted above the second semiconductor chip such that an active region of the third semiconductor chip faces upward;
• a third encapsulation portion formed along an edge of the third semiconductor chip above the second encapsulation portion;
• a third wiring pattern connected to bond pads of the second semiconductor chip, the third wiring pattern formed above the third semiconductor chip and extending above the third encapsulation portion;
• and
• a via contact connecting the first wiring pattern and the third wiring pattern, the via contact formed in the second and third encapsulation portions.

A method of manufacturing a wafer level stacked package with a via contact in an encapsulation portion, the method comprising:

• mounting a plurality of first semiconductor chips on a carrier using an adhesive force such that an active region of the first semiconductor chip faces upward;
• forming a first encapsulation portion having the same height as that of the first semiconductor chip on the carrier;
• forming a first wiring pattern connected to bond pads of the first semiconductor chip, the first wiring pattern extending above the first encapsulation portion;
• mounting a second semiconductor chip on the first semiconductor chip and the first wiring pattern, using an adhesive member, such that an active region of the second semiconductor chip faces upward;
• forming a second encapsulation portion having the same height as that of the second semiconductor chip on the first encapsulation portion;
• forming a via contact by forming a contact hole that exposes the first wiring pattern in the second encapsulation portion and filling the contact hole with a conductive material;
• and
• forming a second wiring pattern connected to bond pads of the second semiconductor chip, the second wiring pattern extending above the second encapsulation portion and electrically connected to the via contact.

A method of manufacturing a wafer level stacked package with a via contact in an encapsulation portion, the method comprising:

• mounting a first semiconductor chip on a carrier such that an active region of the first semiconductor chip faces downward;
• forming a first encapsulation portion completely covering the first semiconductor chip on the carrier;
• removing the carrier and arranging the active region of the first semiconductor chip to face upward;
• forming a first wiring pattern connected to bond pads of the first semiconductor chip and extending above the first encapsulation portion;
• mounting a second semiconductor chip on the first semiconductor chip and the first wiring pattern, using an adhesive member, such that an active region of the second semiconductor chip faces upward;
• forming a second encapsulation portion having the same height as that of the second semiconductor chip on the first encapsulation portion;
• forming a via contact by forming a contact hole that exposes the first wiring pattern in the second encapsulation portion and filling the contact hole with a conductive material;
• and
• forming a second wiring pattern connected to bond pads of the second semiconductor chip, the second wiring pattern extending above the second encapsulation portion and electrically connected to the via contact.

A method of manufacturing a wafer level stacked package with a via contact in an encapsulation portion, the method comprising:

• mounting a plurality of first semiconductor chips on a carrier such that an active region of the first semiconductor chip faces upward, the first semiconductor having a plurality of bond pads;
• forming a first encapsulation portion having the same height as that of the first semiconductor chip on the carrier;
• forming a first wiring pattern connected to one or more of the plurality of bond pads of the first semiconductor chip, the first wiring pattern extending above the first encapsulation portion;
• mounting a second semiconductor chip above the first semiconductor chip, the second semiconductor having a size smaller than that of the first semiconductor chip, the second semiconductor connected one or more of the bond pads of the first semiconductor chip that are not connected to the first wiring pattern;
• forming a second encapsulation portion having the same height as that of the second semiconductor chip, the second encapsulation portion located above the first encapsulation portion;
• mounting a third semiconductor chip above the second semiconductor chip, such that an active region of the third semiconductor chip faces upward;
• forming a third encapsulation portion having the same height as that of the third semiconductor chip, the second encapsulation portion located above the second encapsulation portion;
• forming a via contact by forming a contact hole that exposes the first wiring pattern in the second and third encapsulation portions and filling the contact hole with a conductive material;
• and
• forming a third wiring pattern connected to bond pads of the third semiconductor chip, the third wiring pattern extending above the third encapsulation portion and electrically connected to the via contact.