Substrate for field effect transistor, field effect transistor and method for production thereof

A substrate for a field effect transistor comprising a semiconductor layer and layers having SiO2 layers and Si3N4 layers laminated alternately below the semiconductor layer.

A substrate for a field effect transistor comprising a semiconductor layer, a Si3N4 layer and a SiO2 layer in descending order.

A substrate for a field effect transistor comprising a semiconductor layer, a SiO2 layer, a Si3N4 layer and a SiO2 layer in descending order.

A substrate for a field effect transistor comprising a semiconductor layer, a Si3N4 layer, a SiO2 layer, a Si3N4 layer and a SiO2 layer in descending order.

A substrate for a field effect transistor comprising in descending order a semiconductor layer, a first insulating film layer and an etch stopper layer composed of a material having an etching rate lower than that of the first insulating film layer for etching under a predetermined condition.

A method for production of a field effect transistor in which at least one first insulating film and a semiconductor region provided on the first insulating film are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode provided so as to straddle the first insulating film and the semiconductor region from the upper part of the semiconductor region, and the field effect transistor in which a channel is formed at least on the side surface of the semiconductor region, comprising the steps of:

• (a) etching a substrate having at least a semiconductor layer, a first insulating film layer consisting of one or more layers and an etch stopper layer in descending order, and forming a semiconductor region protruding on the first insulating film layer;
• and
• (b) etching a portion of the first insulating film layer other than the portion provided with the semiconductor region until the etching reaches the etch stopper layer under a condition such that the etching rate of at least the lowermost layer of the first insulating film layer is higher than the etching rate of the etch stopper layer, and providing below the semiconductor region the first insulating film protruding upward from the etch stopper layer.