Ultra-thin body vertical tunneling transistor
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A vertical tunneling, ultra-thin body transistor is formed on a substrate out of a vertical oxide pillar having active regions of opposing conductivity on opposite ends of the pillar. In one embodiment, the source region is a p+ region in the substrate under the pillar and the drain region is an n+ region at the top of the pillar. A gate structure is formed along the pillar sidewalls and over the body layers. The transistor operates by electron tunneling from the source valence band to the gate bias-induced n-type channels, along the ultra-thin silicon bodies, thus resulting in a drain current.
Claims18
A vertical transistor device comprising:
- a pillar formed on a substrate;
- a pair of source regions, having a first conductivity, formed on the substrate and along a lower portion of opposing sidewalls of the pillar;
- ultra-thin silicon bodies formed along a remaining portion of the opposing sidewalls and above and in contact with each source region;
- a drain region formed over and in contact with the pillar and the silicon bodies wherein the drain region is comprised of an opposite conductivity from the source region;
- a gate insulator formed over the pair of source regions, the silicon bodies, and the drain region;
- and
- a gate formed vertically around the gate insulator.
A vertical tunneling, ultra-thin silicon body transistor comprising:
- an oxide pillar formed on a silicon substrate;
- a p+ source region formed on the substrate and a lower portion of opposing sides of the pillar;
- an n+ drain region formed over the top of the pillar;
- an ultra-thin silicon body formed along a remaining upper portion of each opposing side of the pillar between the source region and the drain region;
- an oxide gate dielectric formed around the pillar and the silicon bodies;
- and
- a gate structure formed over the gate dielectric.
A vertical tunneling, ultra-thin silicon body transistor comprising:
- an n-type silicon substrate;
- an oxide pillar formed on the substrate;
- a p+ source region formed on the substrate and vertically along a lower portion of sidewalls of the pillar;
- a lightly doped, p-type silicon body formed around the oxide pillar;
- an n+ drain region formed in a silicon layer on top of the pillar and the silicon body;
- a gate insulator formed around the pillar and over the silicon body, drain region, and source region;
- and
- a surrounding gate structure formed over the gate insulator.
Dependencies are inferred from the claim text.