4f2 self align fin bottom electrodes fet drive phase change memory

A method for manufacturing an array of memory cells on a semiconductor substrate, the method comprising:

• forming a plurality of word lines over a gate dielectric on the semiconductor substrate, the word lines extending in parallel in a first direction, the word lines having word line widths and respective sidewall surfaces;
• forming a sidewall dielectric layer on the sidewall surfaces;
• forming a plurality of pairs of doped regions in the substrate, wherein pairs between adjacent word lines include respective first and second doped regions;
• forming a plurality of bottom electrodes comprising electrode material on the sidewall dielectric layers, first and second bottom electrodes in the plurality of bottom electrodes between adjacent word lines have bottom surfaces in electrical contact with the respective first and second doped regions, and have top surfaces;
• forming a plurality of memory elements comprising programmable resistive material, the memory elements in electrical contact with top surfaces of corresponding bottom electrodes;
• forming a plurality of top electrode structures positioned over and in electrical contact with memory elements in the plurality of memory elements, the top electrode structures having sides extending parallel in a second direction perpendicular to the first direction, and wherein the bottom electrodes in the plurality of bottom electrodes have sides aligned with the sides of the corresponding top electrode structures;
• and
• forming a plurality of dielectric isolation structures wherein the dielectric isolation structures isolate respective pairs of the first and second doped regions between adjacent word lines.

A method for manufacturing an array of memory cells on a semiconductor substrate, the method comprising:

• forming a gate dielectric layer on the substrate, forming a first conductive layer on the gate dielectric layer, forming a second dielectric layer on the first conductive layer, patterning a plurality of strips of photoresist on the second dielectric layer, wherein adjacent strips are separated by a strip separation distance, the strips extending in parallel in a first direction, the strips having strip widths;
• etching the first conductive layer and the second dielectric layer to expose portions of the gate dielectric layer not covered by the strips, thereby forming a plurality of word lines extending in parallel in the first direction, the word lines having respective sidewall surfaces;
• forming a plurality of first doped regions in the substrate using the word lines as masks;
• forming a third dielectric layer on the word lines and the exposed portions of the gate dielectric layer;
• anisotropically etching the third dielectric layer to form a plurality of first word line structures, the encapsulated word line structures defining a plurality of trenches therebetween, wherein the encapsulated word line structures in the plurality of word line structures include (a) a word line from the plurality of word lines, (b) dielectric sidewall spacers on the sidewall surfaces of the word line, (c) a dielectric cap on the word line;
• forming a plurality of second doped regions on or in the substrate within the trenches using the word line structures as masks;
• forming a bottom electrode layer on the word line structures and in alternating trenches in the plurality of trenches;
• etching the bottom electrode layer and the second doped regions in the alternating trenches, thereby forming pairs of bottom electrode structures from the bottom electrode layer and forming pairs of doped regions from the second doped regions, the pairs of doped regions include respective third and fourth doped regions between adjacent word line structures, the pairs of bottom electrode structures include respective first and second bottom electrode structures between adjacent word line structures having bottom surfaces in electrical contact with the respective third and fourth doped regions, the bottom electrode structures having top surfaces;
• forming a layer of programmable resistive memory material on the top surfaces of the bottom electrode structures, the layer of programmable resistive material in electrical contact with the top surfaces of the bottom electrode structures;
• forming a layer of bit line material on the layer of programmable resistive memory material;
• and
• etching to form a plurality of bit lines and a plurality of bottom electrodes, thereby forming an array of memory cells, the bottom electrodes comprising a portion of one of the first or second bottom electrode structures, the bit lines having sides extending in parallel in a second direction perpendicular to the first direction, the bottom electrodes having sides aligned with the sides of the corresponding bit line.