Techniques For Use With Automated Circuit Design and Simulations

An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to generate a description of circuitry that:

• receives a first and a second asynchronous clock signals having a first phase relationship at a first time;
• samples the second clock signal at transitions of the first clock;
• storing the samples;
• and
• analyzes the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship.

A method comprising generating a description of a circuitry that:

• receives a first and a second asynchronous clock signals having a first phase relationship at a first time;
• samples the second clock signal at transitions of the first clock;
• storing the samples;
• and
• analyzes the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship.

An apparatus comprising:

• a receiving circuitry to receive a first and a second asynchronous clock signals having a first phase relationship at a first time;
• a sampling circuitry to sample the second clock signal at transitions of the first clock;
• a storing circuitry to store the samples;
• and
• an analyzing logic to analyze the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship.

A method comprising:

• receiving a first and a second asynchronous clock signals at a first time, wherein the first and second clocks have a first phase relationship at the first time;
• generating an intermediate signal from the second clock signal;
• sampling the intermediate signal at transitions of the first clock signal;
• processing the sampled intermediate signal;
• storing the samples of the processed sampled intermediate signal;
• and
• analyzing the samples to ascertain the phase relationship of the second clock signal with respect to the first clock signal at the first time and provide a representation of the phase representation.

A method comprising generating descriptions of:

• a circuitry to receive a first and a second asynchronous clock signals at a first time, wherein the first and second clocks have a first phase relationship at the first time;
• a circuitry to generate an intermediate signal from the second clock signal;
• a circuitry to sample the intermediate signal at transitions of the first clock signal;
• a circuitry to process the sampled intermediate signal;
• a circuitry to store the samples of the processed sampled intermediate signal;
• and
• an analyzing logic to analyze the samples to ascertain the phase relationship of the second clock signal with respect to the first clock signal at the first time and provide a representation of the phase representation.

An apparatus comprising a machine readable medium that contains instructions which when executed cause a computer to generate descriptions of:

• a circuitry to receive a first and a second asynchronous clock signals at a first time, wherein the first and second clocks have a first phase relationship at the first time;
• a circuitry to generate an intermediate signal from the second clock signal;
• a circuitry to sample the intermediate signal at transitions of the first clock signal;
• a circuitry to process the sampled intermediate signal;
• a circuitry to store the samples of the processed sampled intermediate signal;
• and
• an analyzing logic to analyze the samples to ascertain the phase relationship of the second clock signal with respect to the first clock signal at the first time and provide a representation of the phase representation.

An apparatus comprising:

• a circuitry to receive a first and a second asynchronous clock signals at a first time, wherein the first and second clocks have a first phase relationship at the first time;
• a circuitry to generate an intermediate signal from the second clock signal;
• a circuitry to sample the intermediate signal at transitions of the first clock signal;
• a circuitry to process the sampled intermediate signal;
• a circuitry to store the samples of the processed sampled intermediate signal;
• and
• an analyzing logic to analyze the samples to ascertain the phase relationship of the second clock signal with respect to the first clock signal at the first time and provide a representation of the phase representation.