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US 2008/0313513 A1Published application
Method and Apparatus for Synthesis of Multimode X-Tolerant Compressor
AssigneeSynopsys, Inc.
InventorEmil Gizdarski
Life of this patent
Estimating the term…
Abstract
Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described.
Claims20
A method of compressing test responses of a circuit under test, the circuit under test including a plurality of scan chains which includes a plurality of known scan chains and a plurality of unknown scan chains, the method comprising:
- synthesizing a compressor circuit of the circuit under test according to a selection from a plurality of compressor design strategies, the plurality of compressor design strategies having a varying sensitivity to a quantity of unknown values appearing in the test responses of the circuit under test;
- and the compressor circuit being synthesized selectively compressing the test responses from a plurality of groups of scan chains and a plurality of shift cycles by at least mapping the plurality of scan chains into a plurality of outputs, mapping the plurality of scan chains into the plurality of groups of scan chains, and mapping the plurality of scan chains into a plurality of modes.
wherein the selection is autonomous.
A computer readable medium, comprising:
- computer instructions to perform a method of compressing test responses of a circuit under test, the circuit under test including a plurality of scan chains which includes a plurality of known scan chains and a plurality of unknown scan chains, the method comprising:
- synthesizing a compressor circuit of the circuit under test according to a selection from a plurality of compressor design strategies, the plurality of compressor design strategies having a varying sensitivity to a quantity of unknown values appearing in the test responses of the circuit under test;
- and the compressor circuit being synthesized selectively compressing the test responses from a plurality of groups of scan chains and a plurality of shift cycles by at least mapping the plurality of scan chains into a plurality of outputs, mapping the plurality of scan chains into the plurality of groups of scan chains, and mapping the plurality of scan chains into a plurality of modes.
A computer apparatus, comprising:
- a computer to perform a method of compressing test responses of a circuit under test, the circuit under test including a plurality of scan chains which includes a plurality of known scan chains and a plurality of unknown scan chains, the method comprising:
- synthesizing a compressor circuit of the circuit under test according to a selection from a plurality of compressor design strategies, the plurality of compressor design strategies having a varying sensitivity to a quantity of unknown values appearing in the test responses of the circuit under test;
- and the compressor circuit being synthesized selectively compressing the test responses from a plurality of groups of scan chains and a plurality of shift cycles by at least mapping the plurality of scan chains into a plurality of outputs, mapping the plurality of scan chains into the plurality of groups of scan chains, and mapping the plurality of scan chains into a plurality of modes.
Dependencies are inferred from the claim text.