Debug circuit
OwnerYasushi UEDA, Makoto Okazakiinventors
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Abstract
The present invention provide a debug circuit which has a structure in which a conversion block latches plural internal signals which are supposed to be effective in finding a cause of a malfunction and are outputted from a selection block, using a signal that is outputted from a timing generation block, converts these signals into serial data, and outputs the serial data to an output block, thereby observing plural signals in the LSI using fewer external pins, and performing analysis of the malfunction of the LSI speedy and reliably.
Claims10
A debug circuit that debugs functions of an LSI including a logic circuit which realizes desired logic functions, comprising:
- a selection block for selecting predetermined signals from plural timing signals or plural condition signals which are outputted from the logic circuit;
- a trigger signal generation block for generating a trigger signal on the basis of the predetermined signals that are selected in the selection block, and outputting the same;
- and
- an output block for outputting the predetermined signals that are selected in the selection block and the trigger signal to the outside.
Dependencies are inferred from the claim text.