Programming error correction code into a solid state memory device with varying bits per cell

A method for programming error correction code for a data block into a solid state memory device having a memory array, the method comprising:

• generating a plurality of reliability levels, each with a corresponding bit level, for a plurality of representative cells of the memory array;
• determining a desired reliability level for the error correction code;
• determining an area of the memory array comprising the representative cell having the reliability level of the plurality of reliability levels that is at least substantially equal to the desired reliability level;
• writing the error correction code to the area of the memory array using the corresponding bit level;
• and
• linking the error code to the data block.

A method for programming received data into a data block of a non-volatile memory array, the method comprising:

• determining if the received data is error correction code;
• writing received data that is not error correction code to the data block at a bit level of at least two bits per cell;
• determining a desired reliability level for the received data that is error correction code;
• determining a reliability level for the data block at a first bit level;
• if the reliability level for the data block is at least substantially equal to the desired reliability level, writing the error correction code to the data block at the first bit level;
• if the reliability level for the data block is less than the desired reliability level, decreasing the first bit level to a decreased bit level in order to increase the reliability level to an increased reliability level;
• and
• if the increased reliability level is at least substantially equal to the desired reliability level, writing the correction code to the data block at the decreased bit level.