Processing device and clock control method

A processing device, comprising:

• a CPU;
• an interface for performing data transfer with an external terminal device in synchronization with an external clock supplied from the external terminal device;
• a control circuit that controls the data transfer;
• a clock generation circuit that generates a clock;
• and
• a clock control circuit that switches a system clock used by at least the CPU in the processing device by a command transmitted from the external terminal device between the external clock and an internal clock generated by the clock generation circuit,
• wherein, when the system clock is switched between the external clock and the internal clock, the processing device causes the CPU to be in a sleep state and performs the switching by the clock control circuit, and after the switching is completed, the processing device releases the sleep state of the CPU to restart an operation.

A clock control method in a processing device comprising:

• a CPU;
• a first interface for performing data transfer with an external terminal device in synchronization with an external clock supplied from the external terminal device;
• a control circuit for the first interface;
• a clock generation circuit that generates a clock;
• a second interface for performing data transfer with the external terminal device by using an internal clock generated by the clock generation circuit;
• and a control circuit for the second interface,
• wherein a system clock used by at least the CPU in the processing device is switched between the external clock and the internal clock in accordance with either one of the first and second interfaces used by the processing device in data transfer with the external terminal device, and
• when the system clock is switched between the external clock and the internal clock, the switching is performed after the CPU is caused to be in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart an operation.

A clock control method in a processing device comprising:

• a CPU;
• an interface for performing data transfer with an external terminal device in synchronization with an external clock supplied from the external terminal device;
• a control circuit that controls the data transfer;
• and a clock generation circuit that generates an internal clock,
• wherein a system clock used by at least the CPU in the processing device is switched by a command transmitted from the external terminal device between the external clock and the internal clock, and
• when the system clock is switched between the external clock and the internal clock generated by the clock generation circuit, the CPU is caused to be in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart an operation.

A processing device, comprising:

• a CPU;
• a first interface for performing data transfer with an external terminal device in synchronization with an external clock supplied from the external terminal device;
• a control circuit for the first interface;
• a first clock generation circuit that generates a clock;
• a second interface for performing data transfer with the external terminal device by using a first internal clock generated by the first clock generation circuit;
• a control circuit for the second interface;
• a second clock generation circuit that generates a clock;
• a third interface for performing data transfer with the external terminal device by using a second internal clock generated by the second clock generation circuit;
• a control circuit for the third interface;
• and
• a clock control circuit that switches a system clock used by at least the CPU in the processing device among the external clock, the first internal clock and the second internal clock in accordance with any one of the first, second and third interfaces used by the processing device in data transfer with the external terminal device,
• wherein, when the system clock is switched among the external clock, the first internal clock and the second internal clock, the processing device causes the CPU to be in a sleep state and performs the switching by the clock control circuit, and after the switching is completed, the processing device releases the sleep state of the CPU to restart an operation.