Processor predicting branch from compressed address information

A processor comprising:

• a fetching unit fetching instructions at a fetching stage of a computer that repeats an execution cycle including at least the fetching stage for fetching the instructions from an instruction storage source and an execution stage for processing the instructions;
• an address control unit determining an instruction address defined as a storage source of the instruction fetched by said fetching unit;
• a branch instruction predicting unit predicting, based on history information of the instructions processed in the past, whether the instruction processed by said computer at a next execution stage is a branch instruction or not;
• and
• an execution unit processing at least one of the fetched instructions at the execution stage,
• said address control unit including:
• an encoding unit generating high-order address information by compressing the high-order bit field among a predetermined high-order bit field and a predetermined low-order bit field each contained in the instruction address;
• and
• a restoring unit restoring the high-order bit field from the high-order address information,
• said branch instruction predicting unit including a history storage unit storing the high-order address information and the low-order bit field as history information associated with a branch destination address of the processed branch instruction in any one of a plurality of storage locations that is determined from the high-order address information and the low-order bit field associated with the instruction address of the storage source of the branch instruction.