Coherency maintaining device and coherency maintaining method
AssigneeFujitsu Limited
InventorsHideki Sakata, Hiroyuki Kojima, Masaki Ukai
Life of this patent
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AssigneeFujitsu Limited
InventorsHideki Sakata, Hiroyuki Kojima, Masaki Ukai
Estimating the term…
A second-level cache device stores part of registration information of data for a first-level cache device in a second-level cache-tag unit in association with registration information in a second-level-cache data unit, and stores the registration information of data for the first-level cache device in a first-level cache-tag copying unit. A coherency maintaining processor maintains coherency between the first-level cache device and the second-level cache device based on the information stored in the second-level cache-tag unit and the first-level cache-tag copying unit.
A coherency maintaining device that maintains coherency between a first cache memory and a second cache memory that stores data in the first cache memory, the device comprising:
A coherency maintaining method for maintaining coherency between a first cache memory and a second cache memory that stores data in the first cache memory, the method comprising:
Dependencies are inferred from the claim text.