Semiconductor memory device capable of reading data reliably

A semiconductor memory device comprising:

• a memory cell array in which a plurality of memory cells connected to a plurality of word lines and to a plurality of bit lines are arranged in a matrix;
• a voltage generator circuit which generates potentials for the word lines and the bit lines;
• a data storage circuit which is connected to the bit lines and which stores data to be written to the memory cells or data read from the memory cells;
• and
• a control unit which, in a read operation at a first level generated by the voltage generator circuit, a read operation at a second level, and a read operation at a third level higher than the first level, finds the number of memory cells included between the first level and the second level and the number of memory cells included between the first level and the third level and which determines the result of the read operation at the first level to be read data when (number of memory cells included between first level and second level)/(number of memory cells included between first level and third level) is equal to or smaller than a specified number.

A semiconductor memory device comprising:

• a memory cell array in which a plurality of memory cells connected to a plurality of word lines and to a plurality of bit lines are arranged in a matrix;
• a voltage generator circuit which generates potentials for the word lines and the bit lines;
• a data storage circuit which is connected to the bit lines and which stores data to be written to the memory cells or data read from the memory cells;
• and
• a control unit which controls the voltage generator circuit and the data storage circuit and which sets the threshold voltage of the memory cells at a first level in an erase operation and, according to externally input write data, sets the threshold voltage of the memory cells at the first level, a second level, . . . , an n-th level (n=2k) by repeating a write and verify operation, stores k bits of data, counts a j number of write operations (j is a natural number) for the cells that have exceeded an (h−b)-th level (1≦b≦h, b is a natural number) of the cells to be written at an h-th level (h≦n) after the (h−b)-th level has been exceeded, and makes the writing speed slower or no writing in the j-th and later write operations.

A semiconductor memory device comprising:

• a memory cell array in which a plurality of memory cells connected to a plurality of word lines and to a plurality of bit lines are arranged in a matrix;
• a voltage generator circuit which generates potentials for the word lines and the bit lines;
• a data storage circuit which is connected to the bit lines and which stores data to be written to the memory cells or data read from the memory cells;
• and
• a control unit which controls the voltage generator circuit and the data storage circuit and which sets the threshold voltage of the memory cells at a first level in an erase operation and, according to externally input write data, sets the threshold voltage of the memory cells at the first level, a second level, . . . , an n-th level (n=2k) by repeating a write and verify operation, stores k bits of data, counts an i number of write operations (i is a natural number) from when an (h−c)-th level is exceeded until an (h−b)-th level (1≦b<c<h, b and c are a natural number) is exceeded with respect to the cells to be written at an h-th level (h≦n), and makes the writing speed slower or no writing in the j-th and later write operations (j=i+α) (α is a natural number including “0”) for the cells that have exceeded the (h−b)-th level in a write operation at the h-th level.

A semiconductor memory device comprising:

• a memory cell array in which a plurality of memory cells connected to a plurality of word lines and to a plurality of bit lines are arranged in a matrix;
• a voltage generator circuit which generates potentials for the word lines and the bit lines;
• a data storage circuit which is connected to the bit lines and which stores data to be written to the memory cells or data read from the memory cells;
• and
• a control unit which controls the voltage generator circuit and the data storage circuit and which sets the threshold voltage of the memory cells at a first level in an erase operation and, according to externally input write data, sets the threshold voltage of the memory cells at the first level, a second level, . . . , an n-th level (n=2k) by repeating a write and verify operation in a write operation, stores k bits of data in the memory cells, carries out a verify operation for an n number of levels, the first level, second level, . . . , n-th level (n=2k), in the write operation, and carries out only a verify operation for an h number of levels (h<n) of the n number of levels in the write operation after the input of a first command.

A recording and reproducing system comprising:

• a communication unit which transmits and receives data to and from a data server;
• a reproducing unit which reproduces multimedia data;
• a storage unit which stores the multimedia data;
• and
• a control unit which controls the communication unit, the reproducing unit, and the storage unit and which transmits a multimedia data purchase request to the data server, receives purchase rights data supplied from the data server, and stores the data in the storage unit and, when reproducing the multimedia data, downloads multimedia data corresponding to the purchase rights data stored in the storage unit from the data server, and not only reproduces the downloaded multimedia data at the reproducing unit but also stores the data in the storage unit.